Stimulating Simulating 2: UVM Sequences

Chris Spear, Principle Instructor, presents how to create classes for UVM sequences, which contain one or more transactions. Your testbench needs to send related groups of transactions to verify your design. Next, you will see how a test class starts a sequence. He will explain how transactions flow from the sequence into the rest of the testbench, and how responses flow back. Finally, he will introduce the concept of virtual sequences. What You Will Learn - How to write a simple sequence class in UVM - Why a sequence is built from a task - How a test starts a sequence - How a sequence communicates with an agent, which contains the sequencer and driver - A way for a driver to return a response back to the sequence - Concepts for creating layered stimulus with virtual sequences - Best practices with UVM sequence classes