Renesas Electronics: Ultra-low-power number recognition: Rapid prototyping with Catapult AI NN

Bringing AI models to custom silicon traditionally requires long design cycles and complex hardware design flows. As AI moves toward energy-constrained edge systems, there is increasing demand for approaches that enable both rapid prototyping and strong hardware quality-of-results.

This talk presents the development of a neural network inference accelerator created during the Accelerating Inferencing Using HLS Hackathon organized by Siemens EDA. Starting from a Python model trained on the MNIST dataset, the system was optimized across the full stack, from model tuning and post-training fixed-point quantization to architectural design and High-Level Synthesis targeting a 40 nm ASIC process. The resulting architecture integrates a dedicated inference engine with a lightweight controller based on MicroBlaze to manage data movement and execution.

Despite the rapid development cycle, the final design achieves approximately 96% classification accuracy while consuming 36 µJ per inference under strict performance and area constraints. This work demonstrates how HLS enables efficient co-optimization across the machine-learning and hardware stack, significantly shortening the path from AI models to energy-efficient silicon.