VOIS: Early power estimation to innovation: Open RAN microelectronics case study
This session presents the European project “Malaga R&D microelectronic center”, focused on advancing regional innovation in custom microelectronics. The session outlines the main challenges introduced by Open RAN, where openness, disaggregation, and multi‑vendor interoperability create strict requirements for latency, energy efficiency, and architectural flexibility. At the microelectronic level, these factors intensify power, performance, and design‑space exploration demands for ASIC development. The presentation explains how early PowerPro‑based power estimation and post‑synthesis analysis with Aprisa and PowerPro accelerate the design workflow and support several aspects of the innovation process. We will present on the power saving of several patent-pending techniques targeting AI inference, 5G baseband signal processing, and ASIC‑level control systems, showing how energy‑driven methodologies translate architectural concepts into validated, implementation‑ready designs.
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Gabriel Caffarena
Open RAN Chip Development Manager
Gabriel Caffarena is Open RAN Chip Development Manager at Vodafone Intelligent Solutions, based at Vodafone’s Málaga R&D Center, where he works on the design and implementation of Layer 1 algorithms for 5G/6G and Open RAN chip architectures. He has spent more than two decades in academic positions across Europe, focusing on algorithm to hardware mapping and efficient signal processing architectures.