Smarter timing constraints for Tessent DFT: How Gencellicon simplifies the flow
DFT-related timing constraints can be a significant source of timing closure challenges, especially when created late or managed inconsistently across the design flow. This webinar presents a practical flow integrating Gencellicon with Tessent DFT to enable structured constraint generation, automated validation, and consistent propagation across the design hierarchy. Attendees will learn how this methodology improves constraint quality, reduces debug cycles, and enhances overall implementation predictability.
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Himanshu Bhatnagar
Senior Director
Himanshu brings over 20 years of expertise in chip design, having developed complex SoCs across networking, communications, imaging, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis, a practical guide to synthesis and static timing analysis. Before founding Excellicon, now Gencellicon, Himanshu held key positions at leading semiconductor companies, including Mindspeed Technologies, Conexant Systems, and ST Microelectronics. At Conexant Systems, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally, Himanshu has served as an advisor to various EDA companies.