Solving Timing Closure Challenges using Gencellicon (previously Excellicon)
Timing closure is one of the most challenging aspects of ASIC design. While traditionally seen as a backend process, its resolution begins at the architectural level and extends through the implementation stages. This webinar examines the key obstacles designers encounter and demonstrates how our timing closure solutions deliver comprehensive support throughout the entire design process.
What you will learn:
- The breadth of the entire Gencellicon portfolio
- How timing closure solutions can alleviate your design process using Siemens tools
Who should attend:
- Implementation engineers
- SoC architects
- Design Verification teams
- Test engineers
- Power architects
- Physical designers
Познакомьтесь с докладчиком
Himanshu Bhatnagar
Senior Director
Himanshu brings over 20 years of expertise in chip design, having developed complex SoCs across networking, communications, imaging, and other domains. His extensive experience in SoC realization led to the publication of two books: Advanced ASIC Chip Synthesis, a practical guide to synthesis and static timing analysis. Before founding Excellicon, now Gencellicon, Himanshu held key positions at leading semiconductor companies, including Mindspeed Technologies, Conexant Systems, and ST Microelectronics. At Conexant Systems, he oversaw global implementation efforts and played a pivotal role in establishing multiple design centers in India and China. Additionally, Himanshu has served as an advisor to various EDA companies.