Chiplet-to-Chiplet design with UCIe
The semiconductor industry is shifting rapidly from monolithic SoC design to chiplet-based systems. At the same time, AI compute workloads have pushed into petaflop-class speeds, demanding higher throughput from die-to-die (D2D) connectivity.
UCIe (Universal Chiplet Interconnect Express) delivers the performance, power and area (PPA) advantages needed to meet the demands of tomorrow’s AI workloads. However, to achieve the required performance for next-generation UCIe-based systems, design engineers face significant signal integrity challenges, from crosstalk and reflections to process variation.
This webinar explores emerging D2D connectivity applications and the bandwidth demands that make UCIe signaling a necessity.
What you will learn:
- How to quickly construct and capture die-to-die UCIe interfaces through rapid package assembly pathfinding
- How to optimize system performance, power and area (PPA)
- How shift-left early-analysis methodologies reduce design risk for advanced architectures
- How simulation-to-silicon correlation ensures that design intent translates into reliable hardware
Who should attend:
- IC and IC package verification managers and directors
- IC and IC package design managers
- 3D IC program leads
- CAD and methodology managers
- IC and chiplet designers
- Semiconductor package and substrate designers
- System and micro architects
- Verification engineers working in physical verification and SI/PI
Products covered:
- Innovator3D IC Integrator
- Innovator3D IC Layout
- Innovator3D IC Protocol Analyzer
Познакомьтесь с докладчиками
Keith Felton
Principal Technical Product Manager, Advanced Semiconductor Packaging
Keith Felton is Principal Technical Product Manager, Advanced Semiconductor Packaging at Siemens DISW. He has worked extensively in the area of IC Package design since the late 1980’s. In the early 2000’s he drove the launch of the industries first dedicated System-In-Package design solution. Current activities and focus includes driving the strategy and direction for Siemen’s multi-substrate prototyping, design and verification solution for High Density Advanced Packages. In 2017 he led a team that launched the Siemen’s OSAT Alliance program.
Keith holds a co-inventor patent #8,316,342 – Method and apparatus for concurrent design of modules across different design entry tools targeted to a single layout.
Ahmed ElKhamisi
Application Engineer for 3D IC Packaging
Ahmed ElKhamisi is a 3D-IC Applications Engineer at Siemens EDA, based in Cairo, Egypt. As part of the worldwide technical sales team, he drives technical solutions for advanced packaging and 3D IC design technologies. Ahmed specializes in the Innovator3D IC (i3D) Integrator tool, enabling system-level design and seamless integration into diverse workflows, particularly with Calibre 3DSTACK. Beyond stacking designs, he channels his competitive side through sports.
Bryan McDevitt
Applications Engineer for SI/PI and UCIe Compliance
Bryan McDevitt is an Applications Engineer at Siemens EDA, where he has spent 18 years supporting board- and package-level simulations with the HyperLynx suite of tools. Before moving into applications engineering, he worked as an electrical engineer designing single board computers. In this webinar, he will present the Innovator3D IC Protocol Analyzer portion of the workflow.