On-Demand Webinar

Rapid Power, Performance, & Area Optimization Using HLS

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High-Level Synthesis (HLS) enables the chip designer to effectively explore design alternatives as well as easing today's design reuse challenges. Exploring alternative hardware microarchitectures to determine the optimal power, performance, and area (PPA) of each solution when working at RTL is time-consuming and often impossible.

Further, what is optimal at one semiconductor technology may not be best for another. During this online seminar, we will show how to design for the lowest power hardware using HLS, by first optimizing the microarchitecture and then automatically maximizing clock gating efficiency.

We will show why HLS code is more adaptable to different microarchitectures, design reuse challenges, and geometries, and how using Catapult® HLS with PowerPro® technology, you are able to obtain more optimal low-power designs.

What you will learn:

  • Why many companies shift to HLS

  • HLS design process

  • Algorithm refinement

  • How to represent hardware architecture

  • Microarchitecture transformations

  • HLS optimizations

  • Analysis

  • How HLS addresses RTL reuse limitations

Who should attend:

  • RTL designers

  • Hardware architects

  • Managers interested in moving up to HLS

Agenda:

  • High-Level Synthesis Overview

  • What is different now?

  • Rapid Design Optimization using Catapult HLS 8

  • Design process

  • Functional reuse

  • Conclusion