Design Analyzer Walkthrough Video Series
The following 5-part video series provides a step-by-step walkthrough of how to use Catapult Design Analyzer to analyze and visualize synthesis results, automatically identify the worst coding style mistakes, and pinpoint optimization bottlenecks.
Video 1: Catapult HLS Design Analyzer: Introduction
Catapult HLS Design Analyzer introduction video showing how it can be used to understand how the generated RTL was synthesized from C++/SystemC.
Video 2: Design Advisor
Catapult HLS' Design Advisor demonstrates how it can automatically identify some of the most common, and costly, coding style mistakes.
Video 4: Catapult HLS Design Analyzer Reporting
Catapult HLS Design Analyzer advanced reporting capabilities for both reporting on bill of materials as well as resource sharing are shown in this video.
Video 5: Analyzing Scheduling Failures
This video shows how Design Analyzer can be used to analyze scheduling feedback failures.
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Michael Fingeroff
HLS Technologist
Michael Fingeroff has worked as an HLS Technologist for the Catapult High-Level Synthesis Platform at Siemens Digital Industries Software since 2002. His areas of interest include Machine Learning, DSP, and high-performance video hardware. Prior to working for Siemens Digital Industries Software, he worked as a hardware design engineer developing real-time broadband video systems. Mike Fingeroff received both his bachelor's and master's degrees in electrical engineering from Temple University in 1990 and 1995 respectively.