webinar na żądanie

Using Machine Learning to Verify and Produce Timing Libraries (.libs) 100X Faster for Digital IC Design and Signoff

Udostępnij

Using Machine Learning to Verify and Produce Timing Libraries (.libs) 100X Faster for Digital IC Design and Signoff

Speed up time-to-tapeout with machine learning methods for standard cell, I/O and memory library verification and characterization.

Powiązane treści