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Solutions for the Design and Verification of 5G SoCs

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Design and Verification of 5G SoCs

Webinar Overview

This webinar explains how 5G standards are opening the world of hardware development to anyone that can build the best, cost-effective products. At the heart of many of those products is the system on chip (SoC) that needs to be designed and verified within the context of the overall system. Many companies are involved in 5G SoC development, delivering solutions that match the many configurations needed for different rural and city density requirements. Because there are so many hardware and software configurations and use cases, design and verification of the SoC is critical. That is why Siemens EDA has integrated pre- and post-silicon design and verification solutions.

Attend this webinar to learn how the Catapult HLS platform, Questa verification platform, and Veloce HW-assisted verification system enable integrated and reliable design and verification solutions for 5G system design.

What you will learn

  • Why 5G dramatically increases design complexity
  • How Siemens EDA tools help address the complexity challenges
  • Why Catapult HLS minimizes the issues of changing standards
  • Strategies for reducing project variability with Questa
  • How Veloce helps to maximize your emulation and post-silicon testing environment

    • Who should attend

  • Design engineer
  • RTL designer
  • RTL engineer
  • Verification engineer
  • Validation engineer

    • Poznaj naszych ekspertów

    Siemens EDA

    Ron Squiers

    Solutions Technologist, MED

    Siemens EDA

    Stuart Clubb

    Technical Product Management Director

    Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.

    Siemens EDA

    Joe Hupcey

    ICVS Product Manager

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