On-Demand Webinar

Optimizing SystemC/C++ Hardware Architectures Through High-Level Synthesis


Hardware architecture has a huge impact on RTL "quality of results" when deploying High-Level Synthesis (HLS). In this on-demand seminar, we will cover how to code different hardware architectures in C++ or SystemC to achieve optimal results in the output RTL.

What you will learn:

  • Fundamental filter architectures and HLS coding style

  • Windowing for efficient image processing

  • Delay line implementation with a single-port RAM

Who should attend:

  • RTL designers and managers interested in moving up to HLS

  • Existing HLS users

  • Designers and managers involved in algorithm to RTL translation

  • Hardware architects