On-Demand Webinar

NVIDIA: Design and Verification of a Machine Learning Accelerator SoC Using an Object-Oriented HLS-Based Design Flow

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A high-productivity digital VLSI flow for designing complex SoCs is presented in this webinar. It includes High-Level Synthesis tools, an efficient implementation of Latency-Insensitive Channels, and MatchLib - an object-oriented library of synthesizable SystemC and C++ components. The flow was demonstrated on a programmable machine learning inference accelerator SoC designed in 16nm FinFET technology.

NVIDIA’s DAC Paper: A Modular Digital VLSI Flow for High-Productivity SoC Design.

What you will learn:

  • How to shorten development time & cost

  • A high-productivity digital VLSI flow for designing complex SoCs

  • Efficient implementation of Latency-Insensitive Channels

  • MatchLib - an object-oriented library of synthesizable SystemC and C++ components