Making low power verification debug easy

The increasing demand for high-performance, battery-operated, system-on-chips (SoC) in communication and computing has shifted the focus from traditional constraints (such as area, performance, cost, and reliability) to power consumption. With complex power strategies in place, debugging the power-aware related failures, be it structural or dynamic, poses a big challenge in verification projects. This webinar gives you an overview of low power verification and talks in detail on effective ways to debug common structural and run-time Low Power issues. This webinar will help IP and SOC Design & Verification Engineers and Leads, Project Managers, Verification engineers new to, or exploring low power verification field, Processor verification teams, Verification teams working on IPs or Systems, catering processor and mobile communication space.

What you will learn:

• Low power basics
• Static and Dynamic checks
• Power states
• Debug using Visualizer

Who should attend:

• Verification Engineers
• Project Leads
• CAD Engineers & Managers
• Design Engineers & Managers