LVS debug of today’s complex designs is challenging and time-consuming, but reducing LVS debug time while continuing to provide reliable, high-performance designs is a requirement for chip designers who want to meet their tight tapeout deadlines and satisfy customers.
Siemens EDA is providing new techniques and tools that work together to automated and enhance LVS debugging capabilities, ensuring that their customers can meet market deadlines while maintaining product quality, even for the most advanced designs.
The bad news:
Layout vs. schematic (LVS) comparison is often a tedious and time-consuming process, requiring many debugging iterations and cross-functional interactions before a designer team converges to a LVS-clean design.
The good news:
Siemens EDA is responding with new LVS technology to help designers more quickly and efficiently converge to a LVS-clean design.
What’s emerging are comprehensive LVS debug solutions that can help designers quickly identify and resolve LVS errors. The ideal debug solution would address the two critical issues currently impacting the LVS process of advanced node design verification:
Isolation of connectivity errors found in extraction. By quickly correcting these errors and rerunning LVS, designers can focus most of their time on debugging true comparison errors between the layout netlist and schematic netlist.
A debugging environment that actively helps designers debug LVS discrepancies, and allows cross-probing of LVS discrepancies into design environments.
Let’s take a closer look at why those issues exist, and then we’ll examine some of the new LVS technology helping to resolve them.
What will they learn:
Debug with RVE details
Debug connectivity problems
Debug Device Problems.
Who should attend:
CAD engineers & Managers
Design Engineers & Managers
SOC Engineers & Managers
Physical Verification Engineers & Managers