FinFET technologies reduce leakage, only to have dynamic power increase and become more dominate. This shift makes it even more critical to find new ways to reduce the dynamic power in today’s power sensitive designs.
Designers can achieve substantial reductions by evaluating and selecting optimal microarchitectures for implementing functions in their design.
In this web seminar, we will review:
Alternatives and techniques that can reduce dynamic power
How to select available micro-architectures and the trade-offs and impacts of these decisions
How RTL designers can properly evaluate the trade-offs and make intelligent choices
What you will learn
Techniques to reduce dynamic power by evaluating and selecting optimal microarchitectures to implement functions in their design
The tradeoffs and impacts of these microarchitectures decisions and how RTL designers can choose between them
Who should view
RTL designers interested in maximum reduction of switching/dynamic power in their blocks/designs especially those targeting FinFet technologies
Verification engineers responsible for deeper power reductions
RTL project managers interested in overall power reductions in their designs beyond the typical clock and memory gating.