On-Demand Webinar

Low-Power IP Design – The Key is Catching it Early

Estimated Watching Time: 31 minutes

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In multiple markets, achieving low-power is no longer a “good to have” but a “must have” trait for many IPs. For the most effective low-power design, IPs need to be “low-power qualified” early in the design cycle as power reduction techniques are most effective at the early design stage (during micro-architecting). PowerPro’s “Early Design Checks” for low-power help IP designers easily find structural and functional redundancies in the design and identify and quantify “low-effort, high return” potential power saving opportunities early in the design cycle, even when RTL may be raw and vectors may not be available. IP design teams and management can qualify their IPs for power by specifying objective criteria for these checks and optimizing IPs that fail these checks. IP power can be tracked and the reduction trend may be observed; providing a complete design-for-low-power methodology.

What you will learn:

  • Lint your RTL for Power and generate Power Metrics for establishing low-power qualification criteria

  • Define Key Performance Indicators (KPIs) for low-power design and check if they are met

  • Performing near-sign-off accurate RTL level average and peak power estimation

  • Find Power saving opportunities in your design and fix them (Power Optimization)

  • Run PowerPro in your regression to check if your RTL meets low-power KPIs with every revision

Who should attend:

  • IP Designers

  • RTL Designers/Project leads

  • Low-Power Methodology specialists

  • Design Managers

Meet the speaker

Siemens EDA

Qazi Faheem Ahmed

Principal Product Manager for PowerPro

Qazi is the Principal Product Manager for PowerPro low-power platform at Siemens EDA. He has over 17 years of experience spanning across ASIC/FPGA design and EDA.