Linear Acceleration of HDL Simulation Using Naive Parallel Processing


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This webinar will address how multiprocessor simulation accelerates performance. The results show that when all CPU cores perform equally and the tasks are equally balanced and heavy enough, simulation performance gain will be proportional to the number of used CPUs. 

The push for multiprocessor simulation drives the wish for better performance. While software providers talk about “time to bug” or “time to full coverage”, engineers are interested in cycles per second. They see “oceans” of available CPU cores and the inherent parallel structure of HDL verification tasks as compelling reasons to ask for multiprocessor simulation options. 

The basic ModelSim and Questa were used in this presentation to run basic Verilog test benches. The examples run on a multicore CPU and demand no “exotic” undocumented beta switches or licenses. 


What You Will Learn:

  • When multiprocessor simulation is useful
  • How to avoid common pitfalls of parallel processing
  • How to optimize the usage of available resources for parallel processing


Who Should View:

  • Anyone who has heavy enough simulation to run
  • Anyone who is into parallel processing
  • Anyone concerned with verification of large systems at HDL level
  • HDL verification managers
  • Project managers/technical team leaders


Meet the speakers

Photo of Yehoshua Shoshan

Yehoshua Shoshan

Technical Area Manager

Yehoshua is the Technical Area Manager in Scandinavia with unique knowledge of accelerating verification by parallel processing
Photo of Rick Stroot

Rick Stroot


Rick Stroot is a senior application engineer at InnoFour specialized in the IC, FPGA, Cabling and Application Lifecycle Management products. He has a background in Electronic Engineering specialized in Digital Signal Processing.


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