Webinar about how leveraging HLS IP and reference designs to accelerate AI and Image/Signal Processing.
To accelerate and ease the adoption of HLS, Catapult provides both building block HLS IP and various application reference designs written in C++ or SystemC that are designed to help deliver optimal QofR. This webinar will describe the available IP including the Math and DSP blocks available as open-source and the several reference designs, including 2-D convolution for image enhancements and two CNN (tinyYOLO) implementations for real-time object classification.
This webinar is part 5 of the webinar series: HLS for Vision and Deep Learning Hardware Accelerators
Director of Engineering
David Burnette is currently Director of Engineering for the Catapult High-Level Synthesis product of Siemens EDA. He has contributed to the HLS program over the last 26 years, starting first with behavioral synthesis from VHDL followed by C++/SystemC. Much of his recent work has centered around High-Level Verification (designing infrastructure for comparing the untimed C++ against the timed RTL) and the development of class-based C++ HLS IP for math, DSP/Image Processing and Machine Learning. He received his BSEE and MSEE from Virginia Tech and holds 4 patents in the area of HLS methodologies.