Samsung: Automated bus routing approach for next generation High Bandwidth Memory (HBM) designs
High bandwidth memory (HBM) consists of several memory chips and a dedicated logic base die connected through high-speed parallel signals (Buslines). The throughput of these buslines determines the performance of the HBM. This presentation describes a new automated layout and optimization methodology for the many signal buslines for a next generation HBM. This novel bus delay optimization algorithm in Aprisa delivers a bus layout for an HBM at a fraction of the time that it takes for expert designers to manually guide and test their strict requirements.
발표자 소개
Seyong Ahn
Staff Engineer
Dr. Seyong Ahn received his B.S. and Ph.D. degrees in Electrical and Computer Engineering from Seoul National University, Seoul, South Korea, in 2013 and 2018, respectively. His research focused on resonant clock synthesis methodologies and Design Technology Co-Optimization (DTCO). He is currently a Staff Engineer at Samsung Electronics Memory Division, responsible for physical design methodologies of memory products. He has experience in memory-specific physical design automation and optimization methodologies, and in design technology co-optimization (DTCO) for DRAM and Flash products.