Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL / GDS) RTL lint / formal check tools cannot be run on HLS RTL (as the errors cannot be correlated to HLS source code) Onespin systemC/C++ extension DV help to overcome this challenge. This session will be presented by Siemens on behalf of Infineon Technologies AG.
발표자 소개
Vlada Kalinic
SystemC Product Specialist
Vlada Kalinic is the SystemC Product Specialist at Siemens EDA, and is involved in the evaluations with the new customers as well supporting the current portfolio of the customers to improve the current SystemC flows. Vlada has also another role, as Product Specialist of EC-FPGA in OneSpin. Vlada holds a master’s degree with honors in Electrical and Computer Engineering, Embedded Systems and Algorithms from the University of Novi Sad (Serbia). Prior to Mentor/Siemens, Vlada worked with OneSpin for 5+ years and was involved in various successful evaluations with SystemC and EC-FPGA customers.
관련 자료
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초보자를 위한 MBSE
무료 오디오북을 만나보십시오. Siemens 특별 에디션 도서인 초보자를 위한 MBSE 는 제품 개발 라이프사이클의 모든 요소를 살펴봅니다. 지금 PDF를 다운로드하거나 오디오 버전으로 들어보십시오.