온디맨드 웨비나

High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?

예상 소요 시간: 23분

공유

Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to RTL. In the RTL Design space, we will cover our technology for Power Optimization with PowerPro Designer & Optimizer.
Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to RTL. In the RTL Design space, we will cover our technology for Power Optimization with PowerPro Designer & Optimizer.

We will look at how C++ and SystemC/MatchLib High-Level Synthesis is more than just converting SystemC to RTL. We’ll cover language choice, architecture exploration, power estimation and optimization that all work to deliver competitive RTL in a faster time with lower cost. For those still working in the RTL Design space, we will touch on our leading-edge technology for Power Optimization with PowerPro Designer and Optimizer. You won’t be first, but you don’t have to be last.

발표자 소개

Siemens EDA

Richard Langridge

AE Manager

Richard Langridge works for Siemens EDA as an Application Engineering Manager. Richard has more than 30 years of experience in EDA and design, ranging from RTL Synthesis and Low-Power to High-Level Synthesis (HLS) and Formal Methods. Richard manages Low-Power engagements in a variety of Semiconductor customers.

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Siemens의 선도적인 FMEA 도구를 사용하면 사전에 고급 품질 계획 및 위험 관리를 수행하여 제조 단계에서 생산 전에 결함을 방지하고 시간과 비용을 절약할 수 있습니다.