Porting Vivado HLS Designs to Catapult HLS Platform

High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP) blocks for implementation in digital logic solutions such as Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASICs). FPGA vendors offer HLS tools and using those increases flexibility and productivity over traditional hardware description language (HDL) flows. But employing FPGA vendor-specific tools can limit the portability of the design outside of their ecosystem. To regain the flexibility of targeting a design to another technology requires porting the design from the vendor’s HLS environment into an HLS environment that supports any ASIC or FPGA technology.

What You Will Learn

• How to port an existing HLS design developed within the Xilinx® Vivado® HLS environment into Mentor’s Catapult® HLS Platform
• The differences in libraries and data structures
• How to port optimizations from Vivado to Catapult

Who Should Attend

• Designers who are interested in creating a portable solution of ASIC implementation
• Engineering Managers who want to know how to leverage existing code bases in new technologies
• HLS/RTL designers who are interested in learning about Catapult HLS
• Algorithm Developers
• System Architects