Catapult HLS for RTL Teams - What You Need to Know
Catapult® HLS is a key competitive technology in several emerging markets like machine learning and vision. In this webinar, we cover both an introduction to Catapult HLS and what’s new. In particular, how Catapult is expanding to cover a more complete ecosystem around C-based design and how this solution from Mentor provides benefits to users beyond just synthesis. If you want to know what is new in HLS and might be concerned that your competitors are moving ahead with this technology and you are not, this is your opportunity to connect with the Catapult team.
What you will learn:
- How to adopt HLS and be successful
- HLS tool flow and verification methodology overview
- SystemC vs C++ and why C++ is winning the productivity battle
- Code examples for HLS
Who should attend:
- Engineering Directors who need faster design cycles and lower
verification costs than RTL design provides - RTL Design and verification managers who need to improve team
productivity - RTL Designers concerned that RTL might no longer be enough to
compete
발표자 소개
Stuart Clubb
Technical Product Management Director
Stuart is responsible for Catapult HLS Synthesis and Verification Solutions since July 2017. Prior to this role, Stuart had been successfully managing the North American FAE team for Mentor/Siemens and Calypto Design Systems and was key to the growth achieved for the CSD products after the Calypto acquisition. Moving from the UK in 2001 to work at Mentor Graphics, Stuart held the position of Technical Marketing Engineer, initially on the Precision RTL synthesis product for 6 years and later on Catapult for 5 years. He has held various engineering and application engineering roles ASIC and FPGA RTL hardware design and verification. Stuart graduated from Brunel University, London, with a Bachelors of Science.
관련 자료
Rapid Algorithm to HW: Using HLS for Computer Vision and Deep Learning Seminar
How HLS helps project teams rapidly & accurately explore power/performance of algorithms, quickly get to FPGA implementations to create demonstrator/prototypes & use same source RTL IP for ASIC implementation.
에지 기계 학습: HLS를 이용한 전력 및 성능 최적화
기계 학습을 에지(edge)로 옮기려면 전력과 성능 면에서 중요한 요구사항이 뒤따릅니다. 평범한 상용 솔루션을 사용하는 방안은 실용적이지 않습니다.
AI 가속기 생태계: 개요
Catapult HLS 플랫폼은 AI 설계자들에게 프로젝트를 바로 시작할 수 있는 환경을 제공하는 AI 가속기 생태계를 제시합니다. 이 에코시스템은 IP 라이브러리부터 완전한 툴키트까지의 리소스를 실무 엔지니어에게 제공합니다.