Accelerate time to success using smart methods for DFT chip architecture and validation

Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions can work together to provide a smart DFT plug-and-play architecture for Veloce ICs.

The Veloce hardware-assisted verification system can efficiently handle large, full-chip GLE designs. Tessent Streaming Scan Network (SSN), a once-in-a-decade technology, packetizes test data to dramatically reduce DFT implementation effort and reduce manufacturing test cost. The Veloce DFT application enables SSN, as well as other test functions such as TestKompress, BIST pattern validation, functional fault grading, power profiling and estimation, by accelerating multiple orders of magnitude faster than traditional software simulation. Combining Veloce Strato and Tessent SSN can accelerate your time to DFT success.

Who would benefit from watching Accelerate time to success with smart method for DFT chip architecture:

• DFT Engineers
• DFT Managers
• Product and Test Engineers and Managers

What can you learn from this webinar:

• Introduction to Veloce DFT App and how it helps validate Tessent DFT logic/patterns
• DFT Power Profiling and Fault grading using Veloce Power App
• Applying SSN to solve the Veloce chip design challenges