Quantization of HLS Designs Using Value Range Analysis
Algorithm developers are usually using double precision data types to be able to focus on the mathematical functionality of the algorithm. When this algorithm is implemented as a hardware module, the data accuracy must be reduced to minimum number of bits that still fulfills the system performance requirements. The process of converting the floating-point algorithm to bit-level optimized model is complicated and requires special knowledge. This webinar introduces a simple and robust quantization methodology based on value range analysis.
What You Will Learn
- What is fixed-point conversion a.k.a quantization
- Dynamic and static quantization methods
- Handling special cases
- Using Catapult Value Range Analysis feature for quantizing HLS design
Who Should Attend
- Algorithm developers
- HLS designers
- HW designers
- Verification Engineers
講演者の紹介
Petri Solanti
Senior Application Engineer
Petri Solanti is a senior application engineer at Siemens, with an HLS and low-power tools focus. He is a designer and application engineer with over 25 years of experience in Electronics System-Level design tools and methodologies. His areas of interest include design methodologies from algorithm to RTL, system analysis and HW/SW co-design. Prior to Mentor, Mr. Solanti held application engineer positions at Cadence, CoWare, Synopsys and MathWorks. He received his MScEE degree from Tampere University of Technology, Finland.
関連情報
Accelerated Engineeringソリューションが中小企業にもたらすメリット
Accelerated Engineeringソリューションが中小企業にもたらすメリット
中小企業(SMB)向けのAccelerated Engineering
シーメンスのAccelerated Engineering(AE)は、中小企業が製品の品質を向上させ、迅速に市場投入するのに役立ちます。詳しくはこの電子ブックをご覧ください。
設計者がたどる概念から製造までの道筋
シーメンスデジタルインダストリーズソフトウェアを使用して、概念から製造までのプロセスを4つの完全なステップで進める方法を学びましょう。