High-Level Synthesis Verification Technologies and Techniques
When designing with High-Level Synthesis (HLS) many have questions regarding verification. Waiting to verify until you have post-HLS RTL is too late and too inefficient. This session will describe applying known and trusted static, formal and dynamic approaches to verification performed at the C++ or SystemC HLS level of abstraction.
講演者の紹介
David Aerne
Verification Technologist
Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.
関連情報
多目的なデジタル・ツインをビークルダイナミクスとその先へ活用する
このビデオでは、多目的なデジタル・ツインによって、障害物回避などの高度なアルゴリズムの開発や、安全性と快適性、および操縦時のドライバードライバー体験の検討を行うことで、ADASの制御装置開発のクローズド・ループ性能評価が可能になる様子を紹介します。