Why is CDC Verification for FPGA Designs important

FPGA Designs have become very complex today, most FPGA Designs could be considered System On Chip Designs because they contain multiple complex system components with different protocol interfaces like AMBA, PCIe, Ethernet, USB, just to name a few of the most popular ones. The complexity itself is already a challenge for verification in a fully synchronous design. But the multitude of interfaces in today’s applications implies multiple, asynchronous clock domains. There are well-known techniques how to get data safely from one clock domain to the other. But how can verification show that the clock domain crossings (CDC) have been designed such that data can cross them unchanged? This question needs to be answered especially in safety-critical applications as regular verification by simulation can’t show this.

What you will learn:

This presentation will give a short overview about some effects that
can occur if data crosses clock domain boundaries without special
synchronization and the impact to the function of the design. We will
show how Questa CDC as part of the Questa Verification tool suite can
identify different kinds of CDCs and check that the synchronization
method is appropriate to the kind of data protocol crossing the clock
domain and how to report the results in order to prove that all the
CDCs have been checked for proper functioning.