Rapid Design Space Exploration of AI functions on Lattice FPGAs using Catapult High-Level Synthesis
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology has long development cycles involving defining architecture, doing microarchitecture development using RTL, and performing verification. An agile workflow requires being able to iterate through the architecture and implementation phases quickly to converge towards an efficient design. This is especially true for designing low footprint hardware accelerators on FPGAs, where architectural choices directly impact resource fit feasibility and performance.
Join us as we discuss architectural and microarchitectural design space exploration focusing on the SoftMax function—a key component in many neural networks. We showcase how SoftMax can be targeted on FPGA, balancing performance within tight area and resource budgets for edge deployments. We will use Catapult High-Level Synthesis as we discover its capabilities for data path-oriented hardware designs encountered in vision systems and edge inference engines.
Relatori
Cameron Villone
Product Manager
Cameron has joined Siemens in August 2023 through the Atlas New Graduate Program. Cameron graduated from Rochester Institute of Technology with a Masters Degree in Electrical Engineering focusing on Robotics, Embedded Systems, and Computer Vision. Cameron has held previous student roles at General Motors and Texas Instruments. Cameron is currently working primarily on marketing for low-level power estimation and analysis with the PowerPro team.
Shreedutt Hegde
Senior ML RTL Engineer
Shreedutt Hegde is a Technical Lead at Lattice Semiconductor, where he drives FPGA acceleration for the SensAI ML solution stack. His work focuses on designing efficient, low-power ML accelerators for edge devices, with an emphasis on minimal resource footprint and real-time performance. Shreedutt leads accelerator architecture design and owns the RTL microarchitecture development for implementing ML kernels and operators as custom hardware logic on FPGAs.
Prior to Lattice, Shreedutt spent four years at Velodyne LiDARas an FPGA designer, developing high-throughput signal processing pipelines for LiDAR systems, and optimizing 3D object detection models for point cloud data. He holds a Master’s degree in Electrical and Computer Engineering from Carnegie Mellon University (2017), where he specialized in hardware-software co-design.
Passionate about FPGAs and embedded systems, Shreedutt brings a systems-level perspective to building intelligent, efficient, and scalable ML solutions.
Sivasankar Palaniappan
High-Level Synthesis Technologist
Sivasankar currently works as a High-Level Synthesis Technologist in the Marketing division of the Catapult team. He joined Siemens in July 2020 as an Associate Rotation Engineer and migrated to the new role a year later. Sivasankar has a MS in Electrical and Computer Engineering, focusing on Computer Engineering from University of California San Diego.