Using chiplet design kits to help pave the way for 3D IC heterogeneous integration
A chiplet is an ASIC die specifically designed and optimized for operation within a package in conjunction with other chiplets. Heterogeneous integrated (HI) involves integrating multiple die or chiplets into System-in-Package (SiP) chiplets. These devices offer considerable benefits, including performance, power, area, cost and TTM.
The Chiplet Design Exchange (CDX) consists of EDA vendors, chiplet
providers/assemblers and SiP integrators and is an open working group to recommend standardized chiplet models and workflows to facilitate a chiplet ecosystem. This webinar summarizes the chiplet design kits (CDKs) proposed to help standardize 2.5D and 3.D IC designs to create an open ecosystem.
<h2>Building an ecosystem for successful 2.5D and 3D chiplet model integration</h2>
Similar to an SOC process, you need an ecosystem for chiplets. Key enables for general market adoption and deployment of chiplet based designs include:
- Technology: 2.5 D interposer and 3D stacked die manufacturing and assembly processes
- IP: Standardized chiplet models
- Workflows: EDA design flows and PDK, CDK, DRM & assembly rules
- Business models: chiplet marketplace
The initial focus of the CDX is 2.5D interposer-based chiplet models with 3D to follow. Learn more about these efforts in the webinar.
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