On-Demand Webinar

Introduction to Visualizer for the Verilog Users

Visualizer Debug Environment for Verilog and UVM

Estimated Watching Time: 35 minutes


Questa Visualizer Debug On-Demand Webinar

Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines, including Verilog, VHDL, UVM, SystemC, C/C++, Assertions and Coverage. This session will introduce the Visualizer Debug Environment for Verilog and UVM.

What you will learn:

  • Post-simulation and live-simulation debug

  • Driver tracing and X-tracing

  • Source code debug

  • Waveform debug

  • UVM Debug, including classes and transactions in the waveform

Meet the speaker

Siemens EDA

Rich Edelman

Product Engineer

Rich Edelman is a Product Engineer at Siemens EDA for the Visualizer Debug Environment. He is a verification technologist helping customers adopt successful techniques for UVM and class based testbenches. Rich previous work includes register verification, SystemVerilog DPI development and transaction recording interfaces for Questa. Rich graduated from Washington University in St. Louis with a bachelor's degree in Computer Science, a bachelor's degree in electrical engineering and a master's degree in computer science.