Improve your Debug Productivity

With today’s more complex designs, we tend to see a growing productivity gap between design and verification, so we need to maximize the reusability of your verification environment, improve the automation, raise the level of abstraction… but we need higher performance, context-aware debug supporting the complete logic verification flow.

During this session, we will cover different techniques for debugging your RTL.

Source code while running a live simulation.

What you will learn:

• How to debug complex and mixed verification environments
• How to use a set of synchronized views for analyzing waveforms and
  source code
• How to find (X values) and trace an event back in time
• How to explore the physical connectivity of your design