How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself


Image for How to Exhaustively Verify Register I/O Policies Without Exhausting Yourself event

Even relatively small IPs can have hundreds of control&status registers, many with customized, unconventional access policies. While testbench simulation-based register verification approaches like UVM_REG can exercise most of the primary use cases, numerous corner-cases can be left uncovered, creating the risk of show-stopper bugs going undetected. 

In this webinar, we will show how to employ an automated, formal-based flow to ensure complete coverage of your registers’ state space – without having to learn formal at all. The benefits of this approach are two-fold: you can exhaustively verify the specified behaviors and the complete absence of any illegal behaviors. Plus, any detected discrepancies are graphically shown in detailed waveforms – i.e. no need to back-track through second-order effects – the results shown are exactly the given issue’s root cause. This will be illustrated in the context of a common, real-world verification task that will be familiar to many – verifying an AMBA AXI3 interface.

Note that this webinar will be relatively technical: the examples will include timing diagrams and RTL code. Familiarity with Verilog or VHDL is assumed. 

What You Will Learn:

  • How to exhaustively verify your control&status register behavior against your register specification. This includes both common policies (e.g. R/W, Write to Clear, Read-only, etc.) and user-defined register configuration schemas and access policies
  • How to set up the flow to design and verify front or back-door register access
  • You will actually NOT learn about formal itself – the formal verification is automated under-the-hood 

Who Should Attend:

  • Design & Verification Engineers & Managers

Meet the speakers

Photo of Joon Hong
Siemens EDA

Joon Hong

Questa Formal Product Engineer

Joon Hong is a Product Engineer on the Questa Formal team, with a focus on supporting customers with very large scale SoC ASIC and FPGA design and verification flows. In addition to his formal verification skills, Joon’s background includes simulation-based experience with SVA, UVM, low power (UPF), and clock-domain crossing (CDC) verification. Joon holds a Master's degree focused in Electrical, Electronics and Communications Engineering from Yonsei University.
Photo of Joe Hupcey
Siemens EDA

Joe Hupcey

Questa Formal Product Manager

Joe Hupcey III is a part of the Mentor’s Product Management team for Design & Verification Technologies; based in Mentor’s office in Silicon Valley, CA. He is responsible for the Questa Formal product line of automated applications and advanced property checking. Prior to joining Mentor, Joe has held product management and marketing roles in several Electronic Design Automation (EDA) companies, for products that covered multiple aspects of hardware and software functional verification. Before transitioning into marketing, Joe worked as an electrical engineer in FPGA design, EDA tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes BSEE, MSEE, and MBA degrees from Cornell University in Ithaca, NY.


Register with your Siemens account or register as a guest.