How Integrated FPGA-PCB I/O Co-Design Accelerates PCB Design and Reduces Costs


Image for How Integrated FPGA-PCB I/O Co-Design Accelerates PCB Design and Reduces Costs event
The ability to read in, export and synchronize FPGA designers’ HDL and constraint files ensures full consistency during the iterative concurrent design process. Incidentally, it also allows creating high pin count FPGA PCB parts ready for instantiation in minutes. Modern FPGA I/O optimization helps you not only accelerate design time-to-market, but also reduces manufacturing costs.

Meet the speakers

Olivier Arnaud

A graduate of Institut Suprieur dElectronique de Paris (ISEP) Olivier began his career in 1987 as an Integrated Circuit (IC) designer working on GaAs Broadband amplifiers, RISC microprocessors and Telecom ASICs for large electronic companies such as Philips, Alcatel and Dassault. In 1995 he became an Application Engineer (AE) then worldwide Design For Test consultant for Sunrise Test Systems. In 1998 he joined Escalade, a startup company and specialized in HDL Design tools as the Technical Authority for Europe and Asia. Escalade was acquired by Mentor Graphics in 2000. Upon the acquisition Olivier became AE and subsequently Technical Marketing Engineer (TME) for the HDL Designer product suite, Product Architect in the Board Systems Division working on DxDesigner and xSD System Designer, Product Marketing Manager for FPGA on-board I/O optimization product (I/O Designer I/O Optimizer) and eventually member of the Customer Migration team. Currently he works for Mentors Focus Product Organization as a Senior Application Engineer Consultant. Olivier is based in Mentors Meudon, Paris, Office.


Create or Login with a Siemens account to register for this webinar.