Tessent UltraSight-V – An on-chip debug and trace solution for RISC-V systems
An infrastructure to enable debug and trace for your RISC-V systems is essential to identifying root-causing bugs. In this presentation, we will give an overview of Tessent UltraSight-V, an end-to-end RISC-V debug and trace solution consisting of embedded IPs and software that integrate with industry-standard tools.
We will explain how the integration of UltraSight-V’s on-chip IP modules and host software can empower engineers to efficiently diagnose the root causes of unexpected behavior and underperformance. UltraSight-V uses effective, non-intrusive techniques (such as highly compressed encoded processor instruction trace based on the Efficient Trace (E-trace) standard), logging, high-speed interfaces (USB 2.0) and DMA for fast code uploads. UltraSight-V minimizes debugging delays and accelerates your SoC projects, allowing you to meet market deadlines.
Siemens is a key contributor to the RISC-V Efficient trace (E-trace) specification. This presentation will include a demonstration of the UltraSight-V solution.
What you will learn:
- How UltraSight-V provides extensive insight into a RISC-V SoC for debug and trace purposes
- What the RISC-V Efficient trace (E-trace) standard is and how the Enhanced Trace Encoder in UltraSight-V reduces some of the risks of adopting RISC-V
- How non-intrusive visibility, logging, and fast code uploads mechanisms using the DMA can be used to understand program behavior for advanced debugging and minimize debugging delays
Who should attend:
- SoC Architects
- Software Architects
- Embedded Software Engineers
- Anyone considering or already using RISC-V
À propos des intervenants
Mike Sharp
Product Engineer
Mike Sharp has had a number of technical sales and customer facing roles during his 30 year career in the semiconductor industry. He joined the Tessent Embedded Analytic team in Feb 2019 as Application Engineer providing customers with pre and post-sales support. In May 2024 Mike joined the Tessent Embedded Analytic Product Management team providing a wealth of experience in SoC debug, analytics and performance monitoring.
Dr. Francisca Tan
Product Management Senior Manager
Dr. Francisca Tan is the Product Management Senior Manager for Tessent Embedded Analytics at Siemens EDA. With nearly a decade of experience in the semiconductor industry, she has held various engineering, research, and management roles at Siemens, Arm, and Intel. Her interest encompasses the SoC IP business and ecosystem, embedded system functional monitoring analytics, and Silicon Lifecycle Management. She holds both an MEng and a Ph.D. in Electrical and Electronic Engineering from the University of Nottingham, U.K.