Tessent AnalogTest - Automated test generation for analog & mixed-signal circuits

Virtually all SoCs designed today contain variable amounts of analog / mixed-signal circuitry. Such A/MS cores often lack Design-for-Testability (DFT) features and typically have an unknown defect coverage that is only empirically determined over time, based on product iterations and failure analysis from field returns. Fault coverage in SoCs thus always excludes A/MS circuits. There is a better way to run efficient manufacturing tests that reduce/eliminate test escapes from low-coverage A/MS cores!

Watch this webinar to learn more about how analog test generation can be automated with new EDA tools, thanks to upcoming industry standards. Also find out how digital scan tests and ATPG can be applied to A/MS circuits, as to achieve a high defect coverage AND minimize tester time by orders of magnitude.

This webinar will reduce analog designers’ workload and provide DFT engineers with everything they need to determine comprehensive test coverage metrics for the entire design – not just for digital logic.

What you will learn:

• Learn about IEEE 2427, a standard for Analog Defect Modeling and Coverage
• Learn about IEEE P1687.2, a proposed standard to automate test & measurements and facilitate reuse across A/MS designs
• Learn about Tessent AnalogTest, which leverages the above standards and a novel technique to bring digital scan test and ATPG to A/MS designs

Who should watch:

• Analog designers, Analog DFT engineers who want to obtain the highest test coverage possible for their circuits
• Digital DFT engineers who need to write functional analog tests without having to learn SPICE language
• Test engineers looking for quicker silicon ramp-up, including both digital and analog portions of the chip