Interplane Crosstalk and Dielectric Selection in PCB Stackup Design

As signaling speeds continue to increase, interplane crosstalk, PDN design, and proactive stackup planning are becoming a significant part of the process of designing for signal and power integrity.

Out of necessity, PCB fabricators developed the ability to make dielectric decisions, while adjusting trace widths and spacing to reach target single-ended and differential impedances on signal layers and making stackup design decisions to achieve target board thicknesses. For years, hardware design teams have trusted this process, throwing designs over the wall to fabricators, without the tools, process, or materials knowledge to make the same decisions. As a result, some fabricator proposals are trusted “as is,” and many require days or weeks of back-and-forth email discussions to finalize stackup designs.

PCB fabricators do a great job with impedance. They’ve been designing for impedance for years. But fabricators know little or nothing about a design’s Power Distribution Network (PDN) or crosstalk requirements, treating non-signal layers as generic “planes” rather than power or ground layers that need to be managed separately within the stackup. Along with the fact that hardware design teams are often unaware of the tradeoffs associated with dielectric material choices up and down the stackup, this leads to unintended interplane coupling and intermittent field failures.

This webinar introduces Z-planner, an advanced tool for the design and analysis of PCB stackups. We’ll show you how to create a detailed design that maximizes intentional interplane coupling between power and ground planes (PWR/GND), and minimizes unintended coupling between power layers (PWR/PWR), power and signal layers, and dual-stripline signal layers – while using real materials that fabricators can pull off the shelf and build boards with.

Along the way, we will analyze several real stackup examples where these issues were missed in the stackup design process with Z-planner’s Design for SI utility.

What You Will Learn:

• The interrelationship between board thickness, layer counts, and signal layers
• Best practices for using the Z-direction to manage crosstalk
• Managing crosstalk between dual stripline layers
• Minimizing crosstalk between power planes
• Eliminating crosstalk between power planes and adjacent signals
• Selecting dielectric constructions and glass styles for signal and power integrity
• Automating the stackup design process
• Automating PCB stackup verification for signal integrity and power integrity

Who Should Attend:

• Hardware engineers
• Signal Integrity specialists
• Power Integrity specialists
• PCB layout engineers
• Hardware design managers

Products Covered:

• Z-planner Enterprise