Designing for Low-Power? Glitches Can Ruin your Day!
There is no dearth of low power techniques and RTL designers have been using them to optimize the power of their designs. But with the advent of complex, high-performance designs on lower technology nodes, especially for AI that are computationally intensive, a new power component is surprising RTL designers. Glitches! Up to 40% of the design’s dynamic power could be on account of glitches. Is there a way to identify glitches at the register transfer level? What can RTL designers do about glitches? Join us to learn how glitches can be identified, root-caused and mitigated to avoid late-stage power surprises and enable the delivery of risk free, low-power RTL.
À propos de l'intervenant
Mohammed Fahad
Technical Marketing Engineer
Mohammed Fahad works with Siemens EDA as Technical Marketing Engineer. Fahad has more than 17 years of work experience in the field of Low Power, CDC and FPGA based system design. At Siemens EDA, Fahad is responsible for Low Power technology deployment and proliferation activities across a variety of Semiconductor customer base.