Accelerated HLS Verification with AWS cloud native EC2 instances

High-Level Synthesis enables developers to work at a higher level of abstraction, delivering greater productivity for both design and verification. Verifying at a high level of abstraction, HLS testbenches often use realistic input and large data sets. But verification must also prove correctness at the RTL level. This talk will describe how we used an FPGA on a PCIe card in the AWS cloud to run abstract C++ testbenches against the RTL created using HLS. A common testbench for both the C++ DUT and the generated RTL enabled us to completely reuse code for stimulus and results checking.

Amazon Web Services offers “F2” servers that have AMD VU47P FPGAs on a PCIe card, with DPI and C++ interfaces. The HLS created RTL can be compiled to the FPGA using Vivado synthesis tools. The testbench communicates with the RTL DUT though the C++ interfaces, while running the C++ model in parallel as an oracle. The FPGA delivers much higher RTL performance as compared to logic simulation.