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A Hybrid Design Verification Methodology for Increased Coverage and Faster Iterations

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A Hybrid Design Verification Methodology for Increased Coverage and Faster Iterations

This webinar discusses a hybrid approach for post-route verification that quickly and automatically screens designs for potential faults across multiple disciplines. Potential faults can then be reviewed by the designer and further quantified through simulation if necessary. This method permits near real-time checking of layout as the design progresses. It also eliminates the delays and quality issues associated with manual design reviews while providing complete coverage of high-speed, EMI, and safety layout constraints to ensure all requirements have been satisfied.

Overview

70% of signals in today’s PCB designs require layout constraints for
high-speed signaling, EMI, or safety requirements. Proper
implementation of constraints needs to be verified after layout to
minimize the chance of design errors that could require a re-spin.
Detailed post-route simulation is expertise and time-intensive, and
not all constraints are amenable to simulation. Safety issues like
electrical creepage involve complex non-linear phenomena that are not
easy to simulate. As a result, most companies dedicate their scarce
signal and power integrity specialists to the most challenging
problems and use manual design reviews for everything else – a process
that is both time-consuming and error-prone.

This webinar discusses a hybrid approach for post-route verification
that quickly and automatically screens designs for potential faults
across multiple disciplines. Potential faults can then be reviewed by
the designer and further quantified through simulation if necessary.
This method permits near real-time checking of layout as the design
progresses. It also eliminates the delays and quality issues
associated with manual design reviews while providing complete
coverage of high-speed, and safety layout constraints to ensure all
requirements have been satisfied.

Who should attend:

  • PCB/System Designers
  • Layout Engineers
  • CAD teams responsible for sign-off and review
  • Electrical Engineers
  • Engineering Managers

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