As semiconductor manufacturing technology continues to advance, the size and complexity of integrated-circuit designs grow exponentially. Consequently, the time-to-design-closure of an IC design project becomes not only prolonged, but also uncertain. The impact is especially pressing at digital place & route stage of the design process.
One major factor causing this tremendous difficulty in design closure at advanced nodes is the increasing dominance of resistivity to the signal timing. Capacitance (wire-length) estimation alone is no longer sufficient for precise and correlated timing analysis at early stage of P&R. A paradigm shift to detail-route-centric place and route technology, where detail-route wire/via resistance and signal routing patterns are readily visible to various P&R stages, is needed to alleviate the challenge to design closure.
In this webinar, we will give an overview on Aprisa Detail-Route-Centric Place & Route architecture, a technology recently acquired by Siemens EDA for physical implementation at advanced process nodes. With this technology, timing/power/DRC and other design metrics are consistent throughout the P&R flow, which reduce iterations within the flow, and help to achieve fast time-to-design-closure for your design project.
What you will learn:
Introduction to Aprisa Place & Route tool
Challenges designers face with advanced technology nodes doing P&R
Detail-route-centric architecture to help achieve pre-route to post-route correlation
Sibling route technology to achieve better timing on high performance cores
PowerFirst Technology to optimize best possible power
How to achieve fast time to design closure for your design
Who should attend:
PD/Backend Engineers & Managers
CAD Engineers & Managers
Design Engineers & Managers