Exploration into Safety Analysis Techniques That Optimize the Safety Workflow


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Achieving accurate FIT and DC metrics through structural analysis early in the safety workflow helps validate the safety expert’s initial metric estimates. Attaining an accurate safety level along with automated methods to explore how to improve safeness reduces iterations around costly fault injection. In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.

What You Will Learn:

  • The challenges of achieving ASIL target level
  • Achieving accurate metrics early in the safety workflow
  • A methodology to reduce the number of iterations around fault simulation

 Who Should Attend:

  • Design & Verification Engineers & Managers designing ICs for the autonomous car market
  • Safety Engineers/Experts

Meet the speakers

Photo of Ann Keffer
Siemens EDA

Ann Keffer

Product Manager - Functional Safety Verification Tools

Ann Keffer is the worldwide Product Manager for functional safety verification tools at Siemens EDA.

Ann started her career in R&D as a software developer for Hewlett Packard. After a few years, she moved into application engineering, then product management. She has since led worldwide marketing and product management for companies in the automation, robotics and automotive functional safety verification industries. She joined Siemens EDA in June of 2019.

Photo of Vinayak Desai
Siemens EDA

Vinayak Desai

Product & Solutions Engineer

Vinayak Desai is a Product & Solutions Engineer at Siemens EDA and is responsible for defining the requirements of the new features for Functional Safety technologies. He holds a Master of Science from California State University at Northridge. Prior to Siemens EDA, Vinayak has held various positions at Synopsys, Atrenta, Magma & Cadence as a Field Application Engineer & at Nokia, NXP as a design support engineer.
Photo of Tom Fitzpatrick
Siemens EDA

Tom Fitzpatrick

Strategic Verification Architect

Tom is a Strategic Verification Architect at Siemens Digital Industries Software (Siemens EDA) where he works on developing advanced verification methodologies and educating users and partners on their adoption. He has been a significant contributor to several industry standards, both in Accellera and IEEE, including Verilog 1364, SystemVerilog 1800, UVM 1800.2 and is a founding member and current Vice Chair of the Portable Stimulus Working Group. He is also the 2019 recipient of the Accellera Technical Excellence Award. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification, Portable Stimulus and other functional verification topics, and has produced some of the most popular and successful video training courses on Mentor's Verification Academy website. Tom holds Master’s and Bachelor’s degrees in EE/CS from MIT, is an avid golfer and a huge Boston Red Sox and New England Patriots fan, and has been married to his wife, Dee, for 25 years.


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