Battelle: Around the tapeout in ~ 70 Days
This presentation covers the digital layout process for a tapeout performed by Battelle using the Aprisa digital implementation solution from Siemens. Battelle completed this digital tapeout in approximately 70 days from design start to sign off. This presentation highlights the rapid adoption and strong performance of Aprisa, and the flow built with additional Siemens products, as well as the dedication and collaboration of Battelle and the Siemens engineers that made this achievement possible.
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Vince McKinsey
Lead ASIC Design Engineer
Vince McKinsey is one of Battelle's Lead ASIC Design Engineers. With a Masters in Electrical and Computer Engineering from The Ohio State University, Vince's 6 years of experience at Battelle has had him work in a host of technology spaces from Data Converters, PMICs, and Reverse Engineering Fiducials to Ultra-wide band RF Power Amplifiers and TX/RX RF Chains. He is always seeking to expand his knowledge space, help raise up the next generation of engineers, and meet technical challenges head on. In his spare time, he likes snow boarding, roller skating, and improving his ham radio setup.