Raytheon: Catapult HLS enables rapid and accurate design development
This case study demonstrates how Catapult High Level Synthesis (HLS) enables rapid and accurate hardware design through the implementation of weight generation within the bi-cubic interpolation. By evaluating different levels of bit width specification, the study shows that selectively refining key computations achieves hardware efficiency comparable to hand-optimized RTL while significantly reducing design and verification effort.
The results highlight Catapult HLS as an effective solution for accelerating development without sacrificing accuracy, particularly when productivity and time to market are critical.
Conoce al orador
Jackson Chia
Senior Techical Fellow
Jackson Chia is a Senior Technical Fellow at Raytheon with over 30 years of experience in mil-aero and commercial sectors, specializing in FPGA development, digital subsystem architecture, and high-performance processing for advanced COMMs, RF, and EO/IR sensor platforms. He is recognized as a subject matter expert in ASIC/FPGA design and Digital Worst-Case Circuit Analysis (WCCA), with a proven track record of leading large, multi-disciplinary teams to deliver complex, mission-critical systems. Jackson holds a BSEE and MSEE in Digital Signal Processing from UCLA and a EEE in Communication Sciences from USC.