Tips & tricks you probably didn’t know
Chris Spear, Principle Instructor presents coding guidelines for UVM, the Universal Verification Methodology. He recommends how to create testbench transactions and component classes that are easily debugged and reused. Additional rules are shown for SystemVerilog code to prevent common bugs. These strategies are based on decades of experience with functional verification in Verilog, SystemVerilog, and verification methodologies including UVM, OVM, VMM, and more.
Functional Verification Principal Instructor
Chris brings over twenty five years of EDA expertise to Siemens EDA customers and is currently a Functional Verification Principal Instructor with Mentor Learning Services. Holding a degree in electrical engineering from Cornell University, Chris has developed deep roots in the EDA industry, including as a Principal Application Consultant with Synopsys. Chris is also an industry author, writing the 2012 best-selling “SystemVerilog for Verification” and developing the IEEE standard for random seeding and File I/O PLI package that is part of SystemVerilog. Having taught thousands of engineers around the world, Chris is driven by a passion for learning new techniques and then helping others learn best practices for hardware verification. Outside of work, you may see Chris bicycling over 10,000-foot mountain passes.