STMicroectronics: Turbocharge ASIC TAT & QoR through Gencellicon
SoCs are growing in size and complexity, making hierarchical implementation challenging. Key issues impacting turnaround time (TAT) include:
- Complex Constraint Promotion: Translating block-level timing constraints (SDCs) to accurate top-level SDCs is manual, tedious, and error-prone.
- Escalating Constraint Files: Managing and verifying the high volume of SDC files for numerous blocks and operating modes is difficult and risks inconsistencies.
- Increased Clocking Complexity: Analyzing clock interactions and propagation paths is challenging, often relying on manual, error-prone diagrams, which impacts timing closure and Clock Tree Synthesis (CTS).
This session introduces STMicroelectronics' automated methodology using Gencellicon’s Constraints Builder for SDC generation, Constraints Certifier for verification, and Clock Analyzer for simplified clock analysis. This workflow automates constraint promotion, validates timing intent, detects clocking issues, and guides CTS, ultimately improving Quality of Results (QoR) and significantly reducing ASIC implementation TAT.
Conoce al invitado
Raghubeer Singh
Principal Engineer
With 18 years’ experience designing and validating constraints for synthesis and timing analyses design and verification, FPGA design and SPICE modelling, Raghubeer especially enjoys helping engineers explore new ways to design VLSI flows to facilitate their implementation. He completed Masters in VLSI design in 2006 from CDAC-NOIDA (GGSIP University Delhi) and Masters in Electronics from DDU Gorakhpur in 2003.