Why reset domain crossing verification is an emerging requirement to accelerate design-to-revenue in ASIC developments
The design of quality clock-domain crossings (CDCs) today is aided by the maturity and breadth of CDC analysis and verification tools available. As CDCs are more understood, a new breed of domain crossings introduce challenging issues in the design of ASICs. These are Reset Domain Crossings (RDC), brought on by the rise of increased use of third party IPs, aggressive power management and the increased rise of the use of asynchronous resets. This webinar explores the differences between CDC and RDC analyses, and brings to light the importance of this separate analysis for accelerating design-to-market.
What You Will Learn
- What RDC covers that CDC does not
- How Questa RDC identifies and eliminates RDC errors
- The appropriate time in the development cycle to deploy RDC
Meet the speaker
Kurt Takara
Lead Product Engineer
Kurt Takara is the Lead Product Engineer for Questa CDC+RDC at Siemens EDA, and has over 20 years of experience in engineering design and verification, technical marketing and engineering services. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as 0-In Design Automation, Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.