Verification of HPC protocols – Disruptive technologies changing the datacenter game
Webinar Overview
High Performance Compute architectures are changing, driven by the triple quest: achieve the most favorable economics, provide the highest performance, and leverage the advantage of AI/ML alongside traditional processors. To enable those goals, there are new interconnect protocols, memory solutions, storage connectivity solutions at all levels of the datacenter, from chip thru package, board, backplane, module, rack to facility level. Solutions that change the game for design and verification and demand expertise and comprehensive support from EDA.
What You Will Learn:
The Webinar will be focused on the advances in PCI Express generation 6 protocol, and on the Compute Express Link or CXL protocol, pulling on some common threads: verification strategy for complete PCIe/CXL coverage, verifying interconnect security and integrity with IDE, how interconnect meets memory, and productivity solutions to enable time to market.
Who Should Attend:
- Design and Verification Engineers.
- Design and Verification Lead Engineers.
- Design and Verification Managers.
Meet the speakers
Gordon Allan
Product Manager - Questa Verification IP
Gordon is Product Manager for Questa Verification IP at Siemens Digital Industries Software (formerly Mentor Graphics), focused on delivering advanced verification solutions for complex SoC designs of today and tomorrow as part of Siemens EDA.
Gordon was one of the developers of Accellera UVM, and was responsible for Mentor's UVM/OVM Methodology Cookbooks published on the Verification Academy website and appreciated by over 30,000 engineers worldwide, as well as several conference papers on Verification topics at DVCon and elsewhere.
Prior to joining the EDA industry in 2010 he gained over 18 years of SoC Design and Verification experience in lead engineer and senior consultant roles, working with many of the top semiconductor companies, fabless startups, system houses and EDA companies worldwide and giving him firsthand experience of customers’ challenges from spec to tape out.
Meenakshi Mandi
Product Engineer - PCIe Questa Verification IP
Meenakshi is Product Engineer for PCIe Questa Verification IP at Siemens Digital Industries Software (formerly Mentor Graphics).
Meenakshi is a PCI-SIG member and is contributing actively towards the PCIe specification. She has contributed towards various papers in the EDA space. She has around 4 years of experience in PCIe solutions and SoC verification in Siemens EDA. She has been working with many of the top semiconductor companies, fabless startups, system houses in providing the top-notch support for PCIe Questa Verification IP Deployment.