Adoption of HLS (High-Level Synthesis) continues to grow yet there is also a need for associated HLV (High-Level Verification) methodologies. The motivation for this need is verification at the C++ level (versus RTL) has been shown to reduce overall verification costs by as much as 80%. This webinar introduces Catapult “HLS-Aware” C++/SystemC verification tools and flows that will efficiently help find and eliminate bugs early, ensure C→RTL correctness and rapidly close coverage on both the C++ design source and the HLS-generated RTL.
Dave Aerne is a Verification Technologist within the Calypto Systems Division, focusing on HLV (High-Level Verification) solutions. His particular areas of expertise are the UVM and Verification IP. Prior to joining the EDA industry, he gained over 18 years of SoC Design and Verification experience in various roles at semiconductor companies and fabless startups. Dave received a BSCompE from the University of Illinois at Urbana-Champaign and a MSCompE from National Technological University in Fort Collins, Colorado.