Using high-level synthesis to accelerate computer/machine Vision applications

High-Level Synthesis (HLS) has been used in multiple companies, projects, and designs targeting vision processing for the past several years. HLS adoption continues to grow because it is the fastest way to turn complex algorithms into efficient hardware implementations. HLS creates a methodology that enables design teams to rapidly react to changes in algorithm or functional specifications while still meeting demanding schedules. This webinar steps through the basics of how HLS works and why it is such a good fit for image processing and vision applications, using a practical example vision algorithm.

This webinar is part 2 of the webinar series HLS for Vision and deep learning hardware accelerators.

You will learn:

• How HLS is used to implement a computer vision algorithm in either
  an FPGA or ASIC technology and the trade-offs for power and
  performance.
• How HLS is employed to analyze unique architectures for a very
  energy-efficient inference solution such as a CNN (Convolutional
  Neural Network) from a pre-trained network.
• How to integrate the design created in HLS into a larger system,
  including peripherals, processor, and software.
• How to verify the design in the context of the larger system and how
  to deploy it into an FPGA prototype board.