Resets are required in a design to initialize the hardware and force it into a known state or to recover from an error. Because of design complexity, it is quite common to see designs with millions of registers with resets. However, many of these resets are actually redundant. Unnecessary resets can lead to increased power, area and routing congestion, but knowing which registers do not actually require resets is extremely challenging. In recent years, sequential analysis of the design behavior has emerged as a powerful technique to identify deep redundancies and can be applied to finding these redundant resets.
In this live seminar, we present a novel algorithm which uses observability-based sequential analysis to identify the registers in a design which do not require resets. With the proposed algorithm, we have observed up to 70% of the registers in the design that have redundant resets. Removal of the redundant resets can save up to 22% on power and up to 3% on area.
What you will learn:
How to use observability-based sequential analysis to identify registers in a design which do not require resets
Existing methods of reset optimization and their limitations
The results of applying our redundant-reset-detection algorithm on several industrial designs
Who should attend:
Verification engineers responsible for deeper power reductions
Design project managers interested in overall power reductions in their designs beyond the typical clock and memory gating